The Value-added Cure For Performance Anxiety We satisfy the basic demands of wafer saw, visual inspection and lot qualification. We also furnish the more complex processes of wafer bumping, Chip Scale Packaging (CSP), Tape Carrier Packaging (TCP), Tape Automated Bonding (TAB), Known Good Die (KGD) and upscreening. As well, we know the intricacies of understanding design tradeoffs for specific applications. You may access any of these options by using the navigation system to your left. Capabilities will address our help in design. Wafer Processing will talk about sawing, inspection, etc. Interconnect Solutions discusses CSP, TCP, TAB, etc. and Upscreen & Test will provide information on lot acceptance testing and device test programs, and electrical screening capabilities including burn-in. Then please avail yourself of our Die Map Download.