Services
Element Evaluation / Lot Acceptance Testing (LAT)

Microcircuits and semiconductors are completely tested in packaged part form. However, since our product is un-encapsulated die, we are unable to test 100% of the electrical parameters necessary to ensure a conforming device. In an effort to determine the performance of and get a statistical probability of a diffusion lot of die, the hybrid industry has established methods of lot acceptance testing (LAT).

Lot acceptance testing is a sampling method used to discover if a wafer lot has a reasonable probability that it will meet customer specifications. LATs are performed upon customer request. The request could be in the form of a source control drawing (SCD), customer specification, and/or they may request Element Evaluation per Appendix C of MIL-PRF-38534, Class H (for standard high reliability) or Class K (for space level reliability).

When testing to MIL-PRF-38534 Class H, a 10 piece sample size is used with 0 rejects allowed. The 10 packaged test samples are pulled at random from the lot and subjected to the following tests:

  • Internal visual inspection
  • Final electrical tests at +25°C., minimum and maximum operating temperatures
  • Wire bond evaluation (five die, ten wires)

MIL-PRF-38534, Class K requires a minimum of 10 samples, however 3 test samples from each wafer must be pulled and subjected to a more stringent sequence of tests:

  • Internal visual inspection
  • Constant acceleration
  • Temperature Cycling
  • Interim electrical tests at +25°C., minimum and maximum operating temperatures
  • Burn-in (240 hours)
  • Post burn-in electrical test at +25°C., minimum and maximum operating temperatures
  • Steady state life test (1,000 hours)
  • Final electrical test at +25°C., minimum and maximum operating temperatures
  • Wire bond evaluation (five die, ten wires)
  • Scanning electron microscopy (SEM) of one die from each wafer

In the absence of customer supplied electrical test tables; we test devices to the manufacturer data book or the military slash sheet if one is available.

All requests for lot acceptance testing to either a customer's specification and/or to military specifications must be reviewed by component engineering. The component engineer will evaluate our capability to screen the device to comply with the customer's requirement.

For More Information About Chip Supply Click Here.

7725 N. Orange Blossom Trail Orlando, Florida 32810 | Phone: 407.298.7100 | Fax: 407.290.0164
© Copyright 2009 Chip Supply Inc. | Powered By Solodev